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MOSA
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
3 Stereo Inputs and 4-Channel Outputs Volume, Balance, Fader and Selectable Input Gain
FEATURES
*Operation range : 2.7V~5V *3 stereo inputs with selectable input gain *4 independent speaker controls for fader and balance *Independent mute function *Volume control in 1.25 dB/step *I2C interface *Components less and good PSRR *Housed in SOP20, SSOP20 packages
APPLICATIONS
*Portable audio device *Car stereo audio *Hi-Fi audio system *Cross-reference: PT2313L-20
DESCRIPTION
The MS6720 is a 3 stereo inputs/4-channel outputs digital control audio processor for the low voltage operation. Volume, balance (left/right), and fader (front/rear) processor are incorporated into a single chip. The MS6720 also has selectable input gain. All functions are programmable via the serial I2C bus. The default states of the chip as the power is on are: the volume is -78.75dB, the stereo 4 is selected, all the speakers are mute and the gains of the input stage are 0dB. The stereo 4 is connected internally, but not available on pins.
BLOCK DIAGRAM
LOUT 13 LIN 12
Speaker ATT
17
OUT_LF
Mute
LIN1 LIN2 LIN3
11 10 9
Volume Input Selector &Gain Control
Speaker ATT
15
Mute
OUT_LR
20
Serial Bus Decoder and Latches
SCL 19 SDA 18 DGND
Speaker ATT
RIN3 RIN2 RIN1
6 7 8
Volume
16
OUT_RF
Mute Speaker ATT
Supply
2 3 1 5 4 RIN
14
OUT_RR
Mute
AVDD AGND REF ROUT
REV1.0
1
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MOSA
PIN CONFIGURATION
Symbol REF VDD AGND RIN ROUT RIN3 RIN2 RIN1 LIN3 LIN2 LIN1 LIN LOUT OUT_RR OUT_LR OUT_RF OUT_LF DGND SDA SCL Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description Analog Reference Voltage1/2VDD Supply Input Voltage Analog Ground Audio Processor Right Channel Input
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
REF 1 VDD 2 AGND 3 RIN 4 ROUT 5
20 SCL 19 SDA 18 DGND 17 OUT_LF 16 OUT_RF
Gain Output and Input Selector for Right Channel Right Channel Input 3 Right Channel Input 2 Right Channel Input 1 Left Channel Input 3 Left Channel Input 2 Left Channel Input 1 Audio Processor Left Channel Input Gain Output and Input Selector for Left Channel Right Rear Speaker Output Left Rear Speaker Output Right Front Speaker Output Left Front Speaker Output Digital Ground I2C Data Input I2C Clock Input
MS6720
RIN3 6 RIN2 7 RIN1 8 LIN3 9 LIN2 10 15 OUT_LR 14 OUT_RR 13 LOUT 12 LIN 11 LIN1
SOP20 / SSOP20
ORDERING INFORMATION
Package 20-Pin SOP (lead free) 20-Pin SOP (lead free) 20-Pin SSOP (lead free) 20-Pin SSOP (lead free) RoHS Compliance Part number MS6720GTR MS6720GU MS6720SSGTR MS6720SSGU Packaging Marking MS6720G MS6720G MS6720G MS6720G Transport Media 1k Units Tape and Reel 36 Units Tube 2.5k Units Tape and Reel 56 Units Tube
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VESD TSTG TA TJ TS RTHJA Supply Voltage Electrostatic Handling Storage Temperature Range Operating Ambient Temperature Range Maximum Junction Temperature Soldering Temperature, 10 seconds Thermal Resistance from Junction to Ambient in Free Air SOP20 SSOP20 Parameter Rating 6 -3000 to 3000 -65 to 150 -40 to 85 150 260 210 210 Unit V V /W
REV1.0
2
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MOSA
OPERATING RATINGS
Symbol VDD Supply Voltage Parameter
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Min 2.7
Typ -
Max 5.5
Unit V
5V ELECTRICAL CHARACTERISTICS
(Ta=25, All stages 0dB, f=1kHz, CREF =22uF, refer to the application circuit; unless otherwise specified) Symbol Supply IQ PSRR RIN GIN GSTEP ERRG CRVOL RESVOL ERRVOL Quiescent Current Power Supply Rejection Ratio Input Resistance Input Gain Range Step Resolution Gain Setting error Volume Control Range Volume Step Resolution Volume Setting Error Av = 0 to -40dB Av = -40 to -60dB Attenuation Attenuation VIN=0V CREF = 22uF, f = 100Hz Input 1,2,3 Gain 55 35 0 -0.2 -78.75 -0.5 -1 -37.5 -0.2 (THD+N)/S <0.3% VOUT=2Vpp VOUT=4Vpp 4.3 93 2 12.2 60 50 3.75 0 1.25 0 0 1.25 0 -65 -75 0.0177 97 97 12.5 70 11.25 0.2 0 1 5 0 0.1 -60 0.8 mA dB k dB dB dB dB dB dB dB dB dB dB dB Vpp dB % dB dB V V Parameter Conditions Min Typ Max Unit
Input Selectors
Volume control
Speaker Attenuators CRSPK RESSPK ERRSPK MUTE General VOMAX THD+N S/N CS Bus Input VIH VIL Bus High Input Level Bus Low Input Level Maximum Output Voltage Swing Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Channel Separation Left/Right Speaker Control Range Speaker Step Resolution Speaker Setting Error Output Mute Attenuation
REV1.0
3
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MOSA
2.7V ELECTRICAL CHARACTERISTICS
Symbol Supply IQ PSRR General VOMAX THD+N S/N CS Maximum Output Voltage Swing Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Channel Separation Left/Right Quiescent Current Power Supply Rejection Ratio VIN=0V Parameter
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
(Ta=25, All stages 0dB, f=1kHz, CREF =22uF, refer to the application circuit; unless otherwise specified) Conditions Min 53 90 90 Typ 8.7 58 2.5 -50 0.3 94 94 Max 9 Unit mA dB Vpp dB % dB dB
CREF = 22uF, f = 100Hz (THD+N)/S <0.3% VOUT=2Vpp VOUT=2.5Vpp
TYPICAL PERFORMANCE CHARACTERISTICS
(Ta=25, All stages 0dB, f=1kHz, CREF =22uF, refer to the application circuit; unless otherwise specified)
VDD=2.7V VO=2Vpp
f=1kHz
THD+N (%)
THD+N (%)
f=20kHz
THD+N (%)
f=20Hz
f=20kHz
f=20Hz
VDD=5V VO=2Vpp VDD=5V
f=1kHz VDD=2.7V
VOLUME (dB)
OUTPUT VOLTAGE (dBV)
OUTPUT VOLTAGE (dBV)
THD+N vs. Frequency
THD+N vs. Output Voltage
THD+N vs. Output Voltage
CAP=22uF
CAP=22uF
CHANNEL SEPARATION (dB)
VDD=2.7V VIN=-3dBV
PSRR (dB)
CAP=10uF
PSRR (dB)
CAP=10uF
VDD=5V VRR=-20dBV
VDD=2.7V VRR=-20dBV
VDD=5V VIN=0dBV
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR vs. Frequency
PSRR vs. Frequency
Channel Separation vs. Frequency
REV1.0
4
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MOSA
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
Quiescent Current vs. Supply Voltage
I2C BUS DESCRIPTION
Start and Stop Conditions A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing diagram below.
SCL
SDA
Start
Stop
SCL : Serial Clock Line, SDA : Serial Data Line
Data Validity A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL Data line stable, Data valid Data change allowed
Byte Format Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transmitted first.
REV1.0
5
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MOSA
Acknowledge
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.
SCL 1 2 3 7 8 9
SDA MSB Start Acknowledge
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise, the SDA line will remain at the HIGH level during the ninth (9th) clock pulse. In this case, the master transmitter can generate the STOP information in order to abort the transfer.
Timing of SDA and SCL Bus Lines
SDA tf SCL
tLOW
tr
tSU;DAT
tf
tHD;STA
tSP
tr
tBUF
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
Standard Mode Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL VnH
Parameter
Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 -
Max 100 3.45 1000 300 400 -
Unit kHz us us us us us ns ns ns us us pF V V
SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time: For I2C-bus devices Data-set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line
Noise margin at the LOW level for each connected device (including 0.1VDD hysteresis) Noise margin at the HIGH level for each connected device (including 0.2VDD hysteresis)
REV1.0
6
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MOSA
BUS INTERFACE
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Data are transmitted to and from the MCU to the MS6720 via the SDA and SCL. The SDA and SCL make up the BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage.
VDD
Rp Rp
Pull up resistors
SDA (Serial Data Line)
SCL (Serial Clock Line)
MCU
MS6720
Interface Protocol The format consists of the following *A START condition *A chip address byte including the MS6720 address. (7bits) *The 8th bit of the byte must be "0".(write=0, read=1) *MS6720 must always acknowledge the end of each transmitted byte. *A data sequence (N-bytes + Acknowledge) *A STOP condition
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S START CONDITION ADDRESS
W R / --
P ACK DATA ACK DATA ACK STOP CONDITION
Address Code The chip address of the MS6720 is 88H.
1 0 0 0 1 0 0 0 W
7 bits address MS6720 address
REV1.0
7
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MOSA
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Data Bytes Description The default states of the chip as the power is on are: the volume is -78.75dB, the stereo 4 is selected, all the speakers are mute and the gains of the input stage are 0dB. MSB 0 1 1 1 1 0 0 1 1 0 0 1 B2 0 1 0 1 0 B1 B1 B1 B1 B1 G1 B0 B0 B0 B0 B0 G0 A2 A2 A2 A2 A2 1 A1 A1 A1 A1 A1 S1 LSB A0 A0 A0 A0 A0 S0 Function Volume Control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio Switch
Where Ax = 1.25dB/step; Bx = 10dB/step; Cx = 2dB/step; Gx = 3.75dB/step
Volume MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 The default volume is -78.75dB. B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 Function Volume 1.25 dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70
REV1.0
8
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MOSA
Speaker Attenuator MSB 1 1 1 1 0 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 A2 A2 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
LSB A1 A1 A1 A1 0 0 1 1 0 0 1 1 A0 A0 A0 A0 0 1 0 1 0 1 0 1
FunctiondB Speaker LF Speaker RF Speaker LR Speaker RR 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30
1
1
Mute
LF: Left Front, RF: Right Front, LR: Left Rear, RR: Right Rear The default state is mute.
Audio Switch MSB 0 1 0 G1 G0 1 S1 0 0 1 1 0 0 1 1 0 1 0 1 LSB S0 0 1 0 1 Function Audio Switch Stereo 1 Stereo 2 Stereo 3 *Stereo 4 +11.25dB +7.5dB +3.75dB 0dB
* The stereo 4 is connected internally, but not available on pins. The default state is stereo 4 and gain 0dB.
REV1.0
9
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MOSA
Examples Set Volume at -37.5dB.
MSB Start LSB ACK 0 0 0 Data byte 1 -30dB Volume 1 1
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
MS6720 Address
1
0
ACK
Stop
-7.5dB
Set Speaker RF at -30dB.
MSB Start LSB ACK 1 0 1 Data byte 1 1 0 0 0dB 0 ACK Stop
MS6720 Address
Speaker RF
-30dB
Set Speaker RR in mute-on.
MSB Start LSB ACK 1 1 1 Data byte 1 1 1 Mute 1 1 ACK Stop
MS6720 Address
Speaker RR
Set Stereo 2 Input with gain of +7.5dB
MSB Start LSB ACK 0 1 0 Data byte 0 1 1 0 1 ACK Stop
MS6720 Address
+7.5dB Stereo 2
REV1.0
10
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MOSA
APPLICATION INFORMATION
Basic Application Example
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
MCU
18 19 20
2.2u
13 12
DGND
SCL
SDA
LOUT
LIN
10u 2.2u
11 8 10
OUT_LF LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 OUT_LR
17
10u
15
INPUT
7 9 6
MS6720
OUT_RF
16
OUTPUT 10u
2.2u
10u OUT_RR
AGND
3 14
ROUT
AVDD
2
REF
1
RIN
4
5
22u AVDD 2.2u
REV1.0
11
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MOSA
EXTERNAL DIMENSIONS
SOP20 (300mil)
D
MS6720
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Detail A
Symbol
E H
h x 45 C
A A1 B C e D E H L h
Dimension in mm Min Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 1.27 BSC 12.6 13 7.4 7.60 10.00 10.65 0.40 1.27 0.25 0.75 o o 8 0
Dimension in inch Min Max 0.0926 0.1043 0.004 0.0118 0.013 0.020 0.0091 0.0125 0.050 BSC 0.4961 0.5118 0.2914 0.2992 0.394 0.419 0.016 0.050 0.010 0.029 o o 0 8
A
A1
e
B
0.25mm L Detail A
SSOP20
D
Detail A
Symbol
E1 E
H x 45 c ZD
A2
A 2
e
b
A1
1 R1 L1 R L Detail A
A A1 A2 b c e D E E1 L h L1 ZD R1 R 1 2
Dimension in mm Dimension in inch Min Max Min Max 1.35 1.75 0.053 0.069 0.10 0.25 0.004 0.010 1.50 0.059 0.20 0.30 0.008 0.012 0.18 0.25 0.007 0.010 0.635 BASIC 0.025 BASIC 8.56 8.74 0.337 0.344 5.79 6.20 0.228 0.244 3.81 3.99 0.150 0.157 0.41 1.27 0.016 0.050 0.25 0.50 0.010 0.020 0.254 BASIC 0.010 BASIC 1.4732 REF 0.058 REF 0.20 0.33 0.008 0.013 0.20 0.008 o o o o 0 8 0 8 o o 0 0 o o o o 15 5 15 5
REV1.0
12
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